`include "/home/lab/lab14/Computer_architecture/homwork/mux16_4to1/src/mux16_4to1.v"
`include "/home/lab/lab14/Computer_architecture/homwork/full_adder/src/full_adder16.v"
module pc (input CLK,
                 RESET,
           	 LD,
           input [1:0] PCSEL,
           input [15:0] OFFSET,
           		DIRECT,
           output [15:0] PC_OUT
   );
    wire [15:0] MUX_OUT,Q_OUT,ADDER_OUT;
    assign PC_OUT = Q_OUT;
    mux16_4to1 mux4to1(.D_IN0(ADDER_OUT),
	    	       .D_IN1(OFFSET),
		       .D_IN2(DIRECT),
		       .D_IN3(),
		       .SEL(PCSEL),
		       .D_OUT(MUX_OUT)
	       		);
    full_adder16 adder(.OP_A(Q_OUT),
	    	       .OP_B(16'd1),
		       .CYI(1'b0),
		       .SUM(ADDER_OUT)
	       		);
    pc_register register(.CLK(CLK),
	    		 .RESET(RESET),
			 .LD(LD),
			 .D(MUX_OUT),
			 .Q(Q_OUT)
		 	);
endmodule
    module pc_register(
        input CLK,RESET,LD,
        input [15:0] D,
        output reg [15:0] Q
        );
        always @(posedge CLK) begin
        if (RESET==1'b1) begin
                Q <= {16{1'b0}};
        end          
        else if (LD==1'b1) begin
            Q <= D;
        end
        else if (RESET==1'b0 & LD==1'b0)begin
        Q <= Q;
        end
        
        end
    endmodule
